1. Field of the Invention
The present invention relates to a semiconductor memory device formed on a semiconductor substrate, and more particularly to an asynchronous type static memory device having a precharge signal generating circuit for generating a precharge signal upon a change in address signals.
2. Description of the Related Art
Static memory devices comprise a memory array of memory cells for storing data in the form of binary logic levels. A memory cell to be selected for reading or writing is identified by row and column address applied to the memory. In particular, a memory cell is accessed by means of a word line and a pair of bit lines selected by a row address and a column address, respectively. In operation, each of the bit lines is set at a level according to data stored in the memory cell connected thereto and to a selected word line, and thus if a bit line has a low logic level after reading the data in a first memory cell, this bit line has to change to a high logic level on reading the opposite data from next memory cell. In this case, a significant time is required for the bit line to accomplish such a change in logic levels, thereby limiting the operation speed. In order to avoid the above problem, equalization of potentials at each pair of bit lines is performed prior to each access operation.
In an asynchronous type static memory which does not receive any clock or timing signal, such equalization of the bit lines is performed by detecting change in address signals by an address transition detecting (ATD) circuit. An example of this technique is disclosed in U.S. Pat. No. 4,355,377 issued to Rahul Sud et al. According to this technique, bit lines are equalized in potential before read data out of a memory cell, by a potential-equalizing signal generated in accordance with an output of the ATD circuit which detects the change of an address and generates a one-shot precharge signal, and thereby a reading speed is increased.
Since the memory receives a plurality of address signals and change in any one of the address signals causes the change in the address to be accessed, the ATD circuit is adopted to generate the one-shot precharge signal when any one of the address signals is changed in levels. Therefore, the ATD circuit is constructed by a plurality of detection units and a logical sum (OR) circuit receiving output from all the detection units. Each of the detection units is supplied with each one of address signals, and generates an active level of output signal upon change in levels of the supplied address signal.
The logical sum circuit generates the one-shot precharge signal when at least one of the detection units generates the active level of output signal. The output of the logical sum circuit, i.e. the one-shot precharge signal is applied to all the equalizing or precharge driver circuits provided to the plurality of bit line pairs, and the number of the bit lines of the recent memory having a large memory capacity such as 1 mega bits or more, is very large. Therefore, in the conventional static memory, a length of a control wiring for carrying the one-shot precharge signal to the precharge driver circuit from the ATD circuit, particularly the logical sum circuit is very long. Accordingly, the above control wiring inevitably has a large stray capacitance and a large load capacitance. As a result, it is difficult to apply a sufficient level of the one-shot precharge signal to the precharge drive circuit from the ATD circuit at a high speed through the control wiring, in the conventional memory. Thus, it is difficult to achieve a high speed precharge operation in the conventional memory.